PARALLEL SESSION
A1L-A
Advanced 3D technology for logic and memory devices Session
SALA MAGNA
TUESDAY - 8 September | 11:00 - 13:00
CHAIRS
Mikael Ostling, Guilhem Larrieu
SESSION PROGRAM
11:00 - 11:20
First Demonstration of 3D-Stackable Vertical Single-Crystal Si Channel FeFET with 10ns Immediate Read-After-Write
Runhao Han, Junshuai Chai, Jia Yang, Ruoyao Ji, Tao Hu, Tairan Luo, Min Liao, Xiaoqing Sun, Bao Zhang, Xin Gong, Yong...
11:20 - 11:40
Fabrication of Hybrid Channel CFET Stack by Innovative Wafer-to-Wafer Bonding and Nanosheet Patterning
Fabien Roze, Sylvain Barraud, Jean-Michel Pedini, Vincent Larrey, Frank Fournel, Jean-Michel Hartmann, Karine Abadie,...
11:40 - 12:00
Reliable and High Performance IGZO and In2O3 Transistors via Channel Capping
Cheng-Wei Cheng, Josh Smith, Kishwar Mashooq, Paul Solomon, Ray Watters, Timothy Philicelli, Daniel Piatek, Christian...
12:00 - 12:20
Revealing the True Thermal Limits of Oxide-Channel FeFETs: Gate Stack Versus Channel
Lance Fernandes, Yu-Hsin Kuo, Chengyang Zhang, Priyankka Ravikumar, Dyutimoy Chakraborty, Ranie Jeyakumar, Taeyoung S...
12:20 - 12:40
Relation Between Switching and Conduction Mechanisms in Ferroelectric HZO 3D Capacitors
Constantin Le Grand de Mercey, Terry François, Marios Barlas, Damien Deleruyelle, Kristell Jouannic, Xavier Federspie...
12:40 - 13:00
High Performance and 450℃ Thermal Stability with Ultra-Scaled 20nm Contact Length Enabled by Ru S/D in Vertical Channel-All-Around IGZO FET
Qingding Tong, Yue Zhao, Xufan Li, Chen Gu, Xinlv Duan, Shitong Yin, Congyan Lu, Yu Liu, Jiebin Niu, Kaiping Zhang, S...