PARALLEL SESSION
A1L-F
Efficient Die to Die Wireline Interface Design Session
SALA FALLA
TUESDAY - 8 September | 11:00 - 12:40
CHAIRS
Harijot Singh Bindra
SESSION PROGRAM
11:00 - 11:20
A 24Gb/s/Wire 0.36pJ/Bit Single-Ended PAM4 Transceiver for High Density Die-to-Die Interfaces
Mingyuan Han, Sujay Patel, Ruhao Xia, Mahmoud Khalil, Mohamed Younis, Yongxin Li, Ahmed Abdelrahman, Kyunghwan Min, P...
11:20 - 11:40
A Single-Ended 2-to-32 Gb/s Multi-Lane-Shared EOM with 92% De-Embedding Fidelity for Multi-Standard Chiplet and Memory Interfaces
Xianting Su, Xiaoteng Zhao, Jie Liu, Chenxi Han, Zhicheng Dong, Zekai Yang, Hongyu Su, Lin Wang, Hongzhi Liang, Shubi...
11:40 - 12:00
A 16.5-Tb/s/mm Noise-Tolerant Transceiver with Crosstalk-Equalized Twisted Channel and Paired Pseudo-Differential Signaling
Jun-Soo Park, Sangeun Hong, Sinho Lee, Yoojin Jung, Young-Wook Kim, Ho-Joon Shin, Junhak Kim, Jeonghyeon Lee, Kwanseo...
12:00 - 12:20
A 0.367 pJ/B 18-Gb/s PAM-3 Transmitter Using a Middle-Level-Activated Reverse CMOS Output Driver for Short-Reach Links
Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Songi Cheon, Chanbin Hwang, Myeongju Park, Junyoung Song
12:20 - 12:40
A 16-Gb/s/pin 277-fJ/Bit Edge-Modulated On-Chip Interconnect Transceiver in 28-nm CMOS
Jiyong Park, Jusung Park, Jintae Kim