PARALLEL SESSION
B2L-D
Fractional PLLs and key Building Blocks Session
SALA VICTORIA
WEDNESDAY - 9 September | 13:50 - 15:30
CHAIRS
Luca Bertulessi, Staffan EK
SESSION PROGRAM
13:50 - 14:10
A Sub-mW and Sub-100fsrms Jitter 6.4GHz Fractional-N Hybrid PLL with -260.9dB FoM and a 100MHz Reference in 28nm CMOS
Zhiqiang Huang, Qingxuan Lin
14:10 - 14:30
A Wide-Range, 5.03 ps Resolution Coarse-Fine Noise-Shaping TDC Using a Voltage-Controlled Switched-Ring Oscillator for dToF LiDARs
Chunlin Li, Xiayu Wang, Rui Ma, Jin Hu, Dong Li, Yang Liu, Jiaji Ma, Zhangming Zhu
14:30 - 14:50
A 7GHz Fractional-N Sampling PLL with Differential Self-Normalized Sampling PD Achieving 83.0fs Integrated Jitter
Zezheng Liu, Dingxin Xu, Yuncheng Zhang, Garry Pranata Kusuma, Daxu Zhang, Ashbir Aviat Fadila, Wenqian Wang, Yuang X...
14:50 - 15:10
A Fractional-N DPLL Using a Stochastic TDC
Mohammed Abdulaziz, Staffan Ek, Tony Påhlsson, Peter Nygren, Henrik Sjöland
15:10 - 15:30
A SAW-Referenced PLL Achieving 19.2-fs Jitter in Integer-N Mode and ±1.5-ppm Frequency Stability in Temperature Compensated Fractional-N Mode
Kyu-Jin Choi, Long He, Jiang Gong, Taekwang Jang