PARALLEL SESSION
C1L-D
Wireline Circuit and Signalling Techniques Session
SALA VICTORIA
THURSDAY- 10 September | 10:40 - 12:20
CHAIRS
Armin Tajalli
SESSION PROGRAM
10:40 - 11:00
A 0.075-pJ/b/dB Isolation-Enhanced 56/2-Gb/s Asymmetric SBD Transceiver for 30.2-dB Loss Automotive Links
Huanfa Sun, Shangjie Wei, Yujie Zeng, Zhouchi Duan, Yucong Li, Yu Su, Chengyao Cao, Yukun He, Bingyi Ye, Xiaoyan Gui
11:00 - 11:20
A 3.0 pJ/b 112 Gb/s Wireline Transceiver with 5-Tap DSP-Based TX and Dual-PD-Mode RX in 28-nm CMOS
Ziyi Lin, Haikun Jia, Ruiheng Qiu, Wei Deng, Fuyuan Yang, Chao Xia, Shitu He, Pengwei Liu, Baoyong Chi
11:20 - 11:40
A 37.3-fJ/b/dB 32-Gb/s Baud-Rate Receiver with JTOL-Enhanced CDR Using Phase Tracking Assistance and Embedded Real-Time QEC
Ho-Joon Shin, Suil Kang, Jeonghyeon Lee, Yoojin Jung, Sinho Lee, Haram Ju, Kwang-Ho Lee, Kwanseo Park
11:40 - 12:00
A 12mW 7.8 Gb/s NRZ/PAM-4 Dual-Mode Digital Spectrum Shaping Signaling Transmitter for Multidrop Interfaces in 28 nm CMOS
Donggeon Kim, Yujin Choi, Seoyoung Jang, Eunsoo Lee, Kiarash Gharibdoust, Armin Tajalli, Fatemeh Akbar, Joohyung Chae...
12:00 - 12:20
A 5nm 8-Phase Clock Generator Based on a Feed-Forward Delay Line for 175GSps Wireline ADCs
Angelo Parisi, Adam Cooman, Ewout Martens, Jan Craninckx