top of page

T2

Sensor Transducers and Analog Frond Ends based on Emerging Electronic Devices

14:00 - 17:30

ROOM ALBÈNIZ

CHAIRS

Jens Trommer (Namlab gGmbH, Dresden, DE)

Walter M. Weber (TU Wien, AT)

Giulio Galderisi (Namlab gGmbH, Dresden, DE)

ABSTRACT

With the evolution of electronic systems from a processing information-centric approach to a sensing and actuation-centric future, smart sensors are key enabling technologies for the European semiconductor sector. In our HORIZON Europe Project, SENSOTERIC, we aim to provide such smart sensing solutions by integrating novel emerging transistor functionalities into both the analog sensor front end as well as the sensor transducer itself. This tutorial will cover a) a selection of introductory- level lectures by experts in the fields of emerging devices as well as on analog sensor circuit designs, and b) provide a platform for young scientists to present their results at the intermediate stage of the project, creating a vital discussion and exchange platform. The topics will cover a broad range of scientific topics, including fabrication of emerging reconfigurable devices, analog circuit design for low- power front ends, image pixel sensors, device modelling, characterization, and bio-sensing.

PROGRAM

13:00 - 14:00 

Lunch

​

14:00 - 14:10

Welcome and Introduction of SENSOTERIC

Jens Trommer (Namlab gGmbH, Dresden, DE)

 

14:10 - 14:30

“Guest Invitation” Key considerations for obtaining high performance contact-controlled thin-film transistors

Radu Sporea (University of Surrey, UK)

Source-gated transistors (SGTs) have a relatively long history of development but only recently have mainstream technologies allowed for their effective implementation at scale. This talk is addressed to those interested in efficient analog and mixed signal design with advanced thin-film transistors. They provide a development progression with a forward look toward SGT application to future edge processing of sensor data, signal conditioning, and current-mode driving. Crucially, the concept can be applied in practically any material system. As such, the talk will present the fundamentals of contact effect engineering and modelling, design rules for successful SGT implementation, specifics of performance optimisation in thin-film silicon, organic, and oxide semiconductors, and structural evolutions for additional functionality. Finally, the next step in the evolution of contact-controlled thin-film transistor, the multimodal transistor (MMT) will be briefly introduced. â€‹

​

14:30 - 15:15

Young Scientist Forum – Short 4-5 min Pitch Presentations

 

14:30 – 14:35

Reliability Aspects of Emerging Reconfigurable Devices

Yuxuan He (Namlab gGmbH, Dresden, DE)

 

14:35 – 14:40

Analog Design of Reconfigurable Circuits Utilizing RFETs

Julian Kulenkampff (TU Darmstadt, DE)

 

14:40 – 14:45

Experimental Investigations of Reconfigurable Current Mirrors and Differential Amplifiers

Andreas Fuchsberger (TU Wien, AT)

 

14:45 – 14:50

Improving Reconfigurability and Regulation in Analog Circuits using RFETs

Marrit Jen Hong Li (TU Eindhoven, NL)

 

14:50 – 14:55

Logic-Integrated RFET Biosensors for Multi-Marker Detection

Roberta Grasso, (EPFL Lausanne, CH)

 

14:55 – 15:00

Molecular Sensor Transducer Platform with Reconfigurable Transistors

Hanna Wursag (TU Wien, AT)

 

15:00 – 15:05

In-Sensor Computation Based on Bio-RFET Circuits

Junyian Qian (EPFL Lausanne, CH)

 

15:10 – 15:30

Discuss Young Scientist Work at Posters

Following the Young Scientist Forum presentations, all 7 presenters will be available at their respective posters for in-depth discussion of their work and scientific exchange with interested audiences.

 

16:00 - 16:30

Schottky Barriers and Reconfigurable Field Effect Transistors: A Tutorial.

Giulio Galderisi (Namlab gGmbH, Dresden, DE)

Schottky Barrier Field Effect Transistors (SBFETs) hold the promise of delivering low leakage currents and an advantageous fabrication process with respect to conventional technologies. When gated through multiple independent gates, SBFETs allow to select the carriers involved in the conduction mechanisms and therefore to toggle unipolar n-type or p-type device characteristics at run-time. In this way, Reconfigurable Field Effect Transistors (RFETs) are built. The possibility to reconfigure those transistors make them great candidates for novel applications such as secure hardware computation, while the tunability of their drive current opens up novel approaches in analog circuit design. Moreover, SBFETs are currently under extensive investigation for cryo-electronic applications as well as for bio-sensing. The relevance of these devices is invigorated by their recent integration on 22nm FDSOI industrial technologies operating down to 0.8V. This talk guides both insiders and non-specialist through the different device variants and applications of Schottky Barrier and Reconfigurable Field Effect Transistors.

​

16:30 - 17:00

Reconfigurable Si, Ge, SiGe, GeSn Transistor Technology Platform: Added Functionality for Beyond CMOS and Sensor Readout Applications

Walter M. Weber (TU Wien, AT)

We will report on a versatile device family based on ultrathin sheets of Si, SiGe, GeSn and Ge epitaxially grown on SOI substrates that allow four distinct device realizations Beyond CMOS capabilities.  The devices composed of an intrinsic and isolated channels can be steered to provide a) runtime reconfigurable charge polarity control, merging p- and n-FET functionality in a universal device, b) negative differential resistance (NDR) at room temperature with tunable peak to valley ratios. Reconfigurable field-effect transistors (RFETs) are a novel device concept that allows to fuse n- and p-type transport in a single universal transistor type. As determined by the application of a program gate (PG) electrode. Thereby, limitations of rigid conventional CMOS technologies relying on static operation schemes are overruled. Runtime reconfiguration can be used at a fine grain manner to build generic circuits that define their actual circuit topology by the applied programming signals. Thereby no doping is required, as the charge transport purely relies on the injection capabilities of gated Schottky junctions at source and drain. Changing the PG voltage leads to band-bending and therefore to electrostatic doping, adapting the barrier shape and thus the tunneling transmissibility to the conduction and valence band edges. We will explore novel circuit topologies and concepts that arise from the inherent reconfigurable nature of the devices. Applications for adaptive computing, tunable analog circuits for sensor readout and multi-valued-logic with reduced transistor count and latencies will be discussed.

 

17:00 - 17:30 

Tunable Analog Front Ends and the role of RFETs in enabling improved flexibility

Eugenio Cantatore (Eindhoven University of Technology, NL)

Tunable Analog Front Ends (AFEs) are a very attractive function in energy limited systems such as e.g. sensors for IOT applications. These AFEs can provide different performance points in the energy/accuracy/speed space, depending on the specific sensor and the specific application, thus enabling large gains in design effort and time-to-market, while preserving excellent efficiency in the actual applications. This talk will overview tunable AFEs approaches and provide some discussion of the role that Reconfigurable FETs (RFETs) can have in enabling improved tunability and flexibility in operation.

​

BIOSKETCHES

Radu Sporea

Dr Radu Sporea is Associate Professor in Semiconductor Devices at the University of Surrey, and holds an EPSRC Early Career Fellowship (2021-2026). He was RAEng Research Fellow (2011-2016), EPSRC PhD+ Fellow (2010-2011) and PhD researcher (2006 – 2010). Radu studied Computer Systems Engineering at “Politehnica” University, Bucharest, and worked as Design Engineer for Catalyst Semiconductor Romania on ultra-low-power CMOS analogue circuits. Radu was named EPSRC Rising Star in 2014 and received the I K Brunel Award for Engineering in 2015, the Vice Chancellor’s award for Early Career Teaching in 2017 and the Tony Jeans Inspirational Teaching distinction in 2018. In 2021, he was a finalist for Innovator of the Year prize at Surrey. In 2025, he was awarded the SID Ben Sturgeon Award for early career achievement in the area of information display technologies. His research focuses on advanced thin-film transistors for improved manufacturability, large area sensors and sensor arrays for smart environments, as well as paper-based electronics and physical-digital interaction. He was chair of the IEEE EDS UK and Ireland chapter between 2022 and 2024.

​

​

​Giulio Galderisi

Giulio Galderisi is a Scientist at NaMLab since 2020 and he received his Ph.D. summa cum laude in Electronic Engineering from TU Dresden in 2025. He won the IPFA 2024 Best Paper in Reliability and on the same year he was awarded with the prestigious IEEE Electron Devices Society PhD Fellowship. He is currently co-author of 30+ publications, and his work focuses on emerging transistor technologies such as Reconfigurable Field Effect Transistors (RFETs). 

​

​

​Walter M. Weber

Walter M. Weber is full professor of Nanoelectronics at TU-Wien in Vienna, Austria, and is head of the Institute of Solid State Electronics and the TU-Wien central clean-room facilities, the center of Micro- and Nanostructures ZMNS. He is author / co-author of more than 160 peer-review publications and over 100 conference contributions. W. M. Weber studied Electrical Engineering at TU Munich, Germany, - MsC (2004), PhD (2008)-. From 2002 till 2006 he joined Infineon Technologies AG - Corporate Research Labs in Munich developing technology for nanometer scale multi-gate transistors including finFETs, multibit trigate memory flash and planar double-gate FETs. From 2006 until 2008 he was at the Qimonda AG -Materials Research Department in Munich developing the synthesis of nanowires heterostructures and the conceiving of novel nanowire transistors with reconfigurable polarity. From 2008-19 he was Senior Scientist at NaMLab GmbH in Dresden leading activities on Si/Ge nanowire devices and high-k materials and was responsible for setting-up and coordinating the clean-room semiconductor-fabrication technology. From 2013-19 he acted as Research Group Leader at the excellence cluster cfaed at TU Dresden. Since 2019 he is full professor at the Faculty of Electrical and Information Technology at TU-Wien in Vienna focusing on Beyond-CMOS nanodevices based on Si, Ge, GeSn d 2D materials. He is an IEEE Senior member and has been active in several technical program committees of conferences, including GADEST, ESSERC, DATE, EMRS, DAC and the Nanowire-Week. 

​

​​Eugenio Cantatore

Eugenio Cantatore received his Master’s (cum laude) and Ph.D. Degree in Electrical Engineering from Politecnico di Bari, in 1993 and 1997 respectively. Till 1999 he was fellow at the European Laboratory for Particle Physics (CERN), Geneva. In 1999 he moved to Philips Research, Eindhoven, and in 2007 joined the Eindhoven University of Technology, where he is full professor since 2016 and presently one of the Chairs of the Integrated Circuits group. His research interests include the design and characterization of electronic circuits exploiting emerging technologies and the design of ultra-low power integrated systems. He authored or co-authored more than 250 papers in journals and conference proceedings, and 15 patents. He has been active in the Technical Program Committees of ESSDERC, IWASI, ESSCIRC and ISSCC. At ISSCC he has been chair of the Technology Directions subcommittee, Program Chair and Conference Chair. He has been member at large of the SSCS AdCom, associate editor of the IEEE Transactions on Circuit and Systems I and editor in chief of the IEEE Open Journal of the Solid-State Circuits Society. In 2006 he received the ISSCC Beatrice Winner Award for Editorial Excellence and was nominated in the Scientific American top 50 list. He received the Philips Research Invention Award in 2007, the Best Paper Award from ESSDERC 2012, the Distinguished Technical Paper Award from ISSCC 2015 and several best lecturer awards. He was nominated IEEE Fellow in 2016.

bottom of page