KEYNOTE SPEAKERS
ARYA BEHZAD
Arya Behzad
Arya Behzad is Vice President of R&D Engineering at Broadcom Inc. and an IEEE Fellow. He leads development of connectivity radios, analog front-end and PMU subsystems, as well as broader mixed-signal and analog research, development, and productization across wireless, copper, and fiber communication systems.
He has held engineering leadership and design roles at MicroUnity Systems Engineering, Maxim Integrated, Broadcom, and Apple Inc., contributing to a wide range of wireless and wireline communication systems and ICs. He was named Broadcom Distinguished Engineer and later Broadcom Fellow for his contributions to CMOS RF transceivers and power amplifiers for WLAN.
He has authored numerous technical papers and is the named inventor on over 300 issued U.S. patents. He has taught courses and presented at the IEEE International Solid-State Circuits
Conference (ISSCC) and at universities including UC Berkeley, Caltech, and UCLA, and has served on the technical advisory board of startup companies. He served on the ISSCC Wireless Technical Committee and as Guest Editor and Associate Editor of the IEEE Journal of Solid-State Circuits. His book Wireless LAN Radios: From System Definition to Transistor Design (IEEE Press/Wiley-Interscience) was recognized as an IEEE Communications Society Book of the Month.
He started his studies at Sharif University of Technology. He received the BSEE from Arizona State University as Outstanding Graduate and the MSEE from UC Berkeley, where he worked on the Infopad project under the guidance of the late visionary Prof. Bob Brodersen.
From Air to Copper to Fiber: When Abstraction Boundaries Fail in Modern Communication Systems
Arya Behzad (Broadcom,US)
Tuesday 8 September
09:20 - 10:00
Sala Magna
Chair:
For decades, communication-system design has relied on decomposition: defining clean abstraction boundaries between devices, circuits, channels, and algorithms, and optimizing each block independently. This approach has been effective across a wide range of media—from air to copper to fiber—where well-defined interfaces enabled scalable design and implementation. However, in modern communication systems, these abstractions are increasingly breaking down.
Across wireless, wireline, optical-access, and chip-to-chip systems, performance is now governed by tightly coupled interactions among channel impairments, clock generation, power delivery, package and substrate parasitics, calibration, equalization, precoding, error correction, and other system-level design variables. Systems must decide how to budget for imperfection across domains—through improved devices, higher analog fidelity, tighter references, and stronger power delivery, as well as equalization, coding, calibration, and architectural adaptation.
This talk presents a unified view of modern connectivity as a multi-dimensional optimization problem, highlighting how different communication systems distribute complexity and margin across domains, and why traditional “throw-it-over-the-wall” design methodologies are becoming less effective. It further discusses the growing need for multi-disciplinary CAD frameworks capable of capturing cross-domain interactions and enabling system-level co-optimization. As communication systems become inherently coupled, future progress will depend less on isolated advances within domains and more on our ability to understand and design for interactions between them.
ROBERTO EMILIO LUIGI BEZ
Roberto Emilio Luigi Bez
Roberto Bez is Italy Country Manager at Micron and Senior Director of Storage Strategic Technology. His professional background spans device physics, electrical and physical characterization, modeling, and Non‑Volatile Memory (NVM) technology development, with direct contributions to NOR, NAND, and Phase‑Change Memory (PCM) architectures.
He began his career in 1987 at STMicroelectronics, focusing on device physics and NVM technology integration. In 2008, he joined Numonyx as Fellow, where he led the development of PCM and alternative NVM concepts. From 2010 to 2015, he held roles at Micron as Fellow and Process Integration Director, with responsibilities covering NVM architecture and process integration.
From 2015 to 2019, he served as Senior Vice President of R&D at LFoundry, driving technology diversification across optical sensors and power devices.
Roberto has served on the Technical Committees of IEDM, ESSDERC, EPCOS, and the Symposium on VLSI Technology, and was a member of the ESSDERC/ESSCIRC Steering Committee and the Scientific Advisory Board of NamLab.
He has held academic appointments as Contract Professor of Electron Device Physics at the University of Milan and Lecturer in NVM Devices at the University of Padua, Politecnico di Milano, and the University of Udine.
He received a Laurea degree in Physics from the University of Milan in 1985 and is the author or co‑author of more than 140 peer‑reviewed publications and 60 patents in microelectronics.
Memory for a better world
Roberto Emilio Luigi Bez (Micron Semiconductor, IT)
Tuesday 8 September
16:30 - 17:10
Sala Magna
Chair:
Memories for a Better World explores how memory and storage technologies have become foundational enablers of artificial intelligence and, by extension, of societal progress. Anchored in Micron’s vision of transforming how the world uses information to enrich life for all, the presentation reframes memory as a strategic catalyst that connects data, intelligence, and real‑world impact. It argues that advances in memory performance, bandwidth, density, and power efficiency directly expand the capabilities of AI across domains such as data centers, healthcare, autonomous systems, smart manufacturing, and climate modeling. The keynote highlights that AI already delivers for the semiconductor industry measurable gains in productivity, yield, and operational safety, while also addressing the growing sustainability challenges of AI infrastructure, including energy use, water consumption, and e‑waste. By showcasing low‑power and high‑bandwidth memory innovations alongside ambitious environmental commitments, the talk positions memory technology as a key lever for enabling AI at scale—responsibly, efficiently, and with meaningful human impact.
RAINER MINIXHOFER
Rainer Minixhofer
Rainer Minixhofer was born in Linz, Austria. He received his M.S. degree in technical physics from the University of Technology Graz, Austria, in 1995 and his PhD degree in microelectronics from the University of Technology Vienna, Austria in 2006. Currently, he is Engineering Fellow at ams AG focusing on novel detector and emitter systems and spectrometers. His scientific interests are process & device simulation of semiconductors, specialized emitter/sensor system solutions and photonics. Rainer has authored/co-authored about 80 publications (ResearchGate) and holds about 30 published patents (18 of them US patents: Link). He is Senior Member of IEEE and Senior Member of Optica. He has served as member of the technical committees of various conferences like the International Electron Devices Meeting or the Micro and Nano Engineering Eurosensors Conference, to name a few.
System Integration Considerations in Electro-Optical Sensor Systems
Rainer Minixhofer (ams OSRAM, DE)
Tuesday 8 September
17:10 - 17:50
Sala Magna
Chair:
The integration of electro‑optical sensor systems with spectrometer functionality into compact mobile system platforms increasingly demands co‑optimization across optics, electronics, and packaging. This work highlights key system‑level considerations for applications such as display management, biosensing and handheld devices in the consumer, medical or industrial field. Challenges in optical coupling, signal-to-noise ratio optimization, and spectral calibration within constrained form factors are addressed. Furthermore, heterogeneous integration approaches that combine photodetectors, filters, illumination sources, photonic circuits and control-ASICs to achieve robust performance across diverse operating environments are discussed. The presented system design principles provide a practical framework for developing next‑generation electro‑optical sensor systems suited for high‑volume and emerging applications..
IOANNIS KABITOGLOU
Ioannis Kabitoglou
Ioannis Kabitoglou heads Infineon’s global business with security solutions for a broad array of applications spanning smartcards and identity documents, embedded security for the IoT, as well as trusted sensing and localization on the basis of Ultra Wideband. Born and raised in Greece, he holds a degree in electrical engineering and information technology from the Technical University in Munich and has been with Infineon for over 25 years. Past positions include a.o. Head of Integrated Sensor Business, Director of Business Planning & Analysis and Marketing Manager for 32-bit Microcontroller & DSP Cores.
Towards a quantum-resilient future
Ioannis Kabitoglou (Infineon, DE)
Tuesday 8 September
17:50- 18:30
Sala Magna
Chair:
As Q-Day is gradually but steadily approaching, Infineon is shaping both the technologies at the heart of quantum computers as well as the technologies at the heart of post quantum cryptography. This keynote will introduce Infineon’s innovation in quantum processing with special focus of ion traps and discuss the quantum threat for cryptography and its implications in connection with legislation. It will explore post-quantum cryptographic schemes and the major challenges in their implementation and deployment and show paths how to master those challenges on hardware and software level.
REGINA DITTMANN
Regina Dittmann
Regina Dittmann is Director of the Peter Grünberg Institute 7 at Forschungszentrum Jülich, one of the pioneering groups in memristive devices and their application in RRAM and neuromorphic circuits. She is internationally recognized for her expertise in the growth of oxide thin films and in elucidating the operating and failure mechanisms of memristive devices.
She received her degree in Physics from the University of Cologne in 1990 and her PhD in Physics from the University of Giessen in 1994. In 2001, she was awarded a Young Investigator Group grant at Forschungszentrum Jülich, followed by a W2/W3 grant from the Helmholtz Association in 2011. Since November 2012, she has also been a Professor at the Faculty of Electrical Engineering and Information Technology at RWTH Aachen University. In 2022, she was appointed Lise Meitner Guest Professor at the Faculty of Engineering at Lund University, Sweden.
Regina Dittmann has co-authored more than 300 scientific publications. Her seminal paper on redox-based resistive switching and nanoionic mechanisms has been cited over 6,000 times. She has served as coordinator and principal investigator in numerous national and international projects, including as co-speaker of the Collaborative Research Centre SFB “Nanoswitches,” funded by the German Research Foundation. Since 2025, she has been coordinating the NEURTEC project, a joint initiative about memristor-based neuromorphic computing between RWTH Aachen University and Research Centre Jülich.
Embracing Ion Dynamics: CMOS-integrated Memristors for Neuro-Inspired Circuits
Regina Dittmann (Forschungszentrum Jülich, DE)
Wednesday 9 September
08:30 - 09:10
Sala Magna
Chair:
Memristive crossbar arrays based on valence change mechanism (VCM) resistive random-access memory (RRAM) are considered a promising solution to overcome the latency and energy limitations of von Neumann architectures for neural network training and inference. In this talk, we present a comprehensive study of VCM-based devices and 1T1R arrays, addressing key challenges in reliability, linear programming, multilevel operation, and circuit-level integration. We demonstrate their capability for in-memory vector–matrix multiplication, and demonstrate novel pathways for spatio-temporal processing for bio-inspired computing.
Precise control of intermediate conductance states is essential for multi-bit storage and synaptic weight representation. We demonstrate that both pulse amplitude and timing enable controlled modulation of the conductance window, allowing stable multilevel programming. The coupling between electrical excitation and thermal dynamics introduces temperature as an additional state variable, enabling the coexistence of long-term potentiation (LTP) and short-term plasticity (STP), and thus supporting dynamic, history-dependent learning functionalities.
Analog neuromorphic computing requires gradual and linear conductance updates. However, filamentary VCM devices typically exhibit abrupt SET transitions due to electrothermal feedback. By applying sub-100 ps voltage pulses to Pt/TaOx/Ta/Pt devices, we suppress this feedback and achieve highly linear potentiation (R² = 99.5% over more than 100 pulses). Using advanced measurement techniques enabling conductance extraction down to 50 ps, we further show that reducing pulse delays below ~250 ps leads to thermal accumulation. This results in frequency-dependent potentiation, where switching dynamics accelerate and linearity can be tuned via pulse timing.
The performance of 1T1R cells is governed by the interaction between the nonlinear RRAM device and the access transistor. Crossbar arrays co-integrated with CMOS were investigated for different transistor geometries, providing design guidelines for resistance window control and application compatibility. Functional validation through vector–matrix multiplication confirms their suitability for in-memory computing, while negligible cell-to-cell interference supports scalability. A method to extract intrinsic I–V characteristics of the RRAM cell from 1T1R measurements is introduced, enabling detailed analysis of voltage drops across both elements. The results show that the operating point of the voltage divider can be tuned between linear and saturation regimes of the transistor, strongly influencing switching kinetics. Trade-offs arise between low-current SET and high-current RESET requirements; as a potential solution, a 2T1R architecture combining high- and low-drive transistors is proposed to decouple these constraints.
In summary, this work provides a unified understanding of VCM-based memristive devices across device, circuit, and array levels, establishing key design guidelines for reliable, linear, and multilevel operation toward scalable neuromorphic hardware.
BERNHARD WICHT
Bernhard Wicht
Bernhard Wicht has more than 25 years of experience in analog and power management IC design. He received his Dipl.-Ing. degree from TU Dresden in 1996 and his Ph.D. (Summa Cum Laude) from TU Munich in 2002. From 2003 to 2010, he was with Texas Instruments, where he designed automotive power management ICs. He is currently the head of the Chair for Mixed-Signal IC Design at Leibniz University Hannover. Dr. Wicht is a co-recipient of various awards, including the 2015 ESSCIRC Best Paper Award. He holds 21 patents. Dr. Wicht has been a member of the ISSCC Technical Program Committee, serving as the Power Management Subcommittee Chair from 2023 to 2026. He was a Distinguished Lecturer of the IEEE Solid-State Circuits Society and General Chair of the International Workshop on Power Supply on Chip (PwrSoC). His book “Design of Power Management Integrated Circuits” received the Wiley–IEEE Press Professional Book Award 2025.
Moore's Law vs. Ohm's Law: Power Management Challenges for High-Performance Computing
Bernhard Wicht (Leibniz University Hannover, DE)
Wednesday 9 September
09:10 - 09:50
Sala Magna
Chair:
This talk explores the current and emerging challenges in power management IC design across various applications, highlighting the complex requirements of high-performance computing. With the progression of Moore’s law, GPU cores demand supply currents of >1000A from sub-1V supplies. Providing these from 48V+ rails requires vertical power delivery through advanced 3D assembly with micro-ohm interconnect resistance. Power conversion techniques are evolving, using hybrid architectures that combine switched-capacitor designs with inductors to deliver power more efficiently. Innovations in integrated voltage regulators (IVRs) featuring embedded passives achieve high current densities, high efficiency, and fast transient response. GaN wide-bandgap semiconductors enable faster, more efficient switching in a compact form factor and can be adopted for both high and low voltages. Both classic CMOS and GaN will be necessary to reconcile Moore’s law with Ohm’s law.
CÉDRIC VIRMONTOIS
Cédric Virmontois
Cédric Virmontois (S’10–M’12–SM’19) received the Engineering degree in Physics from the Institut National des Sciences Appliquées (INSA), Toulouse, France, in 2008, and the Ph.D. degree in Microelectronics from the Institut Supérieur de l’Aéronautique et de l’Espace (ISAE-Supaero), Toulouse, France, in 2012. His doctoral research focused on displacement damage–induced degradation mechanisms in CMOS image sensors. He developed models to characterize the degradation of key sensor performance parameters, particularly dark current and its associated random telegraph signal (RTS), and derived hardening-by-design techniques to mitigate space radiation effects in CMOS imagers. He is currently with the Centre National d’Études Spatiales (CNES), Toulouse, France, within the Technology and Digital Directorate. From 2012 to 2018, he served as a Detection Chain Specialist, where he contributed to the development of imaging systems for future space missions, including electro-optical characterization, analysis, and testing of image sensors. His research activities have since expanded to various solid-state imaging technologies dedicated to visible and infrared applications, leveraging both ground-based and in-flight data to establish generic methodologies for predicting and mitigating space radiation effects. Since 2019, he has been recognized as a CNES Expert in solid-state image sensors and radiation effects. Since 2021, he has served as Head of the Optoelectronic Detection Department.
Detectors and Image Sensors for space applications
Cédric Virmontois (CNES, FR)
Thursday 10 September
09:00 - 09:40
Sala Magna
Chair:
Space imaging has undergone remarkable progress over the past decades, driven by the continuous evolution of detector technologies and image sensors. From visible imaging to infrared and ultraviolet observations, advances in sensor performance have enabled increasingly ambitious scientific and operational missions, expanding our understanding of the Earth, the Solar System, and the Universe.
In this presentation, Cedric Virmontois will provide an overview of the evolution of detectors and image sensors developed for space imaging instruments dedicated to Earth observation, planetary exploration, and astrophysics. The talk will highlight how mission objectives and environmental constraints have shaped detector architectures, performance requirements, and technology roadmaps across a broad range of wavelengths.
The presentation will begin with an overview of the different categories of space imaging missions and their associated requirements. Earth observation missions demand high spatial resolution, large swath coverage, radiometric accuracy, and long-term stability to monitor climate, natural resources, agriculture, oceans, and atmospheric composition. Planetary exploration missions face additional challenges such as extreme radiation environments, low-light conditions, and the need for highly reliable and compact imaging systems. Scientific observatories dedicated to astronomy and cosmology require detectors with exceptional sensitivity, ultra-low noise, and high dynamic range to observe faint objects across the electromagnetic spectrum.
Through representative mission examples and detector developments, this presentation aims to provide a broad perspective on how image sensor technologies have evolved to support increasingly demanding applications in Earth observation, planetology, and space science. It will conclude with an outlook on future detector innovations that are expected to enable the next generation of imaging instruments for space exploration and scientific discovery.
CESC GUIM
Cesc Guim
Cesc Guim is a technologist, researcher, and entrepreneur with a PhD in Architecture and Computer Science. He spent 5 years at BSC researching on HPC. He has >60 publications and tutored several PhDs. He moved to Intel Product Group and then into Intel Data Center and AI. He has been Senior Principal Engineer and Chief Systems Architect for Network and Edge in Intel's Network and Edge CTO Office. He holds over 500 patents. Lead Architect in multiple Intel products and top Intel Inventor (2019)
Design Space Exploration or Design Space Denial? The Case for Rethinking Chip-to-System Co-Design in the Agentic Era
Cesc Guim (Openchip, ES)
Thursday 10 September
09:40 - 10:20
Sala Magna
Chair:
For the past decade, design space exploration for AI silicon has converged on a comfortable and well-understood target: dense or sparse transformer inference and training, optimized for throughput and memory bandwidth in the data center. Our DSE tools, benchmarks, and abstractions have been shaped — and arguably narrowed — by that target. Two accelerating trends now call that convergence into question. Agentic AI systems replace single-shot inference with long-running, tool-using, multi-step reasoning loops, shifting the real bottlenecks toward memory hierarchy, interconnect, and latency variance rather than raw compute. Physical AI and world models push AI workloads out of the data center entirely, into real-time, power- and safety-constrained environments where the trade-off space — latency, determinism, energy — looks nothing like cloud inference.
This talk asks an uncomfortable question: are we still exploring a design space, or have we settled into exploring a comfortable subset of a much larger one? It examines where today's chip-to-system methodologies — fixed dataflows, cloud-centric memory hierarchies, homogeneous compute assumptions — are already showing cracks under agentic and physical AI workloads, and what a genuinely reopened design space would need to look like across the full edge-to-cloud continuum, from transistor-level choices to system architecture. Drawing on first-hand experience building a RISC-V-based AI silicon platform from the ground up, the talk will surface concrete architectural tensions — vector/scalar interface design, memory bandwidth versus compute density, heterogeneous integration — and close with an open challenge to the room: which of our current DSE assumptions are helping us, and which are simply the walls of the box we've stopped noticing we're in.”