14:00-14:20

From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML

Roberto Tinti, Keysight

 

14:20-14:50

From Device Degradation to Circuit Reliability: Aging Models for Predictive SPICE Simulation

Petr Hanys, OnSemi

This paper covers a workflow for compact aging model development including degradation characterization, model formulation, parameter extraction, SPICE implementation, and validation. The methodology targets the dominant MOSFET aging mechanisms, namely HCI, NBTI, and PBTI, and incorporates measurement techniques required for accurate characterization of long-term degradation and recovery effects. Customized model formulations are introduced to describe technology-specific behavior. Validation on devices and representative circuits demonstrates the capability of the models to predict long-term performance degradation in reliability simulations.
 

14:50-15:20

Compact Modeling and Multi-scales Approaches for Radiation Hardening and Hardware Security

Neil Rostand, CEA-Leti

This presentation focuses on compact modeling recently performed at CEA for simulating radiation effects on micro-nano electronic devices and circuits. This work is aiming to develop multi-scales simulation methods for radiation hardening and hardware security. Both single event effects, as heavy-ion or near infrared laser induced Single Event Transient (SET), or cumulative effects as Total Ionizing Dose (TID) effects, will be addressed to give an insight on the modeling approach, the Verilog-A implementation, and the validation of these models.

 

15:20– 15:40

Coffee break

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15:40-16:10

Emerging Challenges in Power Semiconductor Device Modeling – From Data Centers to Electric Vehicles

Miguel Martins, Infineon

Several markets have been booming well above average market growth, among them data centers for AI applications and automotive, especially electric autos. This growth has also impacted on the semiconductor market, affecting several domains, including power semiconductors. One part of the semiconductor development chain is the modeling of the semiconductor devices, which is also affected by the above market growth. In this talk we want to give some insights into the actual challenges of power device modeling.
 

16:10-16:40

From Faster Measurements to Smarter Diagnostics: Machine Learning for Next-Generation E-Test

Jerome Mitard, imec

Advanced transistor architectures, such as nanosheet and complementary FETs (CFETs), increase the volume and complexity of electrical-characterization data. This talk presents two machine-learning approaches to make e-test more efficient and actionable. First, active sampling combined with Gaussian Process Regression dynamically selects the most informative gate-voltage points and reconstructs complete Id–Vg characteristics, reducing measurement effort while preserving parameter accuracy. Second, a Convolutional Neural Network automatically classifies transistor transfer characteristics and identifies distinct failure signatures across wafers with process variations. Together, they form a path from exhaustive testing towards adaptive measurement and automated diagnostics, enabling faster learning cycles and targeted process optimization.

 

16:40-17:10

Development and Integration of an ML-based Surrogate Model for RF Passive Devices in a Commercial RF CAD Flow to Enable an RFIC Design Agent

Romain Demarchi, STMicroelectronics

​With the introduction of generative AI tools, the CAD industry has entered a new direction on improving integrated-circuit design. Machine-learning-based surrogate models play a key role in developing an RFIC design agent by bridging the gap between time-consuming electromagnetic simulations and rapid, data-driven design iteration. In this work, surrogate modeling of integrated inductors is used to predict frequency-dependent behavior from geometry, reducing reliance on simulation and tuning. By combining automated virtual prototyping with machine-learning methods in Python, this approach lays the foundation for inverse design and more autonomous RFIC design flows. Moreover, we discuss integrating the developed models into aa RF CAD environment, such as Keysight ADS/Nexus, to support practical deployment. This can shorten development cycles, reduce design costs, increase reuse of RF passive knowledge, and accelerate the delivery of optimized, high-performance components.

 

17:20-17:30

Panel Session