09:30 - 10:15

Introduction to In-Memory Computing: Recent Prototype Chips and Agentic Co-Design Flow

Shimeng Yu (Georgia Tech, Atlanta, US)

This tutorial reviews recent advances in both analog and digital in-memory computing (IMC) using silicon CMOS technologies and emerging memory devices. We begin by introducing the fundamentals of IMC, including key performance metrics and benchmarking methodologies. Next, we present multiple generations of silicon-proven prototype chips, including current-domain IMC based on resistive random-access memory (RRAM) fabricated in a TSMC 40 nm process, as well as current-domain IMC using ferroelectric field-effect transistors (FeFET) implemented on GlobalFoundries’ 28 nm FeFET platform. We discuss the key challenges of analog IMC, particularly accuracy degradation due to process–voltage–temperature (PVT) variations, along with corresponding mitigation techniques. We then motivate the transition toward more robust digital compute-in-memory (DCIM) architectures, exemplified by FeFET-based divider bit cells, and explore more energy-efficient charge-domain IMC paradigms enabled by ferroelectric non-volatile capacitors (nvCap). Finally, we introduce an agentic co-design workflow using ChatNeuroSim, a cross-layer automation framework built upon the widely used NeuroSim platform. This workflow enables systematic optimization of power, performance, and area (PPA) metrics for IMC architectures under given workload and design constraints.

 

10:15 - 11:00

In-Memory Computing for Trustworthy Edge AI: From Bayesian Methods to On-Chip Learning

Elisa Vianello (CEA-Leti, Grenoble, FR)

The deployment of artificial intelligence (AI) on edge devices requires performing complex tasks under strict energy and latency constraints. This challenge has driven significant interest in in-memory and near-memory computing paradigms, which aim to reduce data movement and improve efficiency. However, beyond efficiency, ensuring the trustworthiness of AI systems remains a critical concern. Conventional neural networks often lack mechanisms to quantify prediction uncertainty, making them vulnerable in safety-critical applications. Bayesian neural networks offer a promising alternative by enabling principled uncertainty estimation. In this context, emerging nanodevices with intrinsic stochasticity can be leveraged to perform Bayesian in-memory computing. By encoding probability distributions at the device level, such approaches naturally provide uncertainty estimates while reducing the overhead associated with deterministic implementations. Another key challenge is the reliance on cloud-based training, where edge devices depend on shared datasets and pre-trained models. On-chip learning addresses this limitation by enabling local adaptation directly on inference hardware, thereby reducing data transfer, enhancing privacy, and improving robustness. This tutorial reviews recent hardware innovations, including hybrid synaptic architectures that decouple inference from learning, as well as algorithmic approaches such as meta-learning, which combine global cloud-based training with efficient on-device adaptation.

 

11:00 – 11:30

Coffee break

 

11:30 – 12:15

In-Memory Analog Computing for AI and Neuromorphic Accelerators

Zhong Sun (Peking University, Beijing, CN)

The rapid growth of artificial intelligence (AI), including deep neural networks and large language models (LLMs), is placing increasing demands on computing performance and energy efficiency. Conventional digital processors are fundamentally limited by the von Neumann bottleneck, where data movement between memory and compute units dominates power consumption and latency. In-memory computing (IMC) offers a promising solution by performing computation directly within memory arrays, thereby reducing data movement and enabling massive parallelism.

This tutorial introduces analog and mixed-signal IMC architectures based on emerging resistive memory devices, such as resistive RAM (ReRAM) and phase-change memory (PCM). These devices exhibit two fundamental characteristics—static conductance and dynamic switching—both of which can serve as computing primitives for accelerating AI algorithms. In particular, many AI workloads are dominated by linear algebra operations, such as matrix–vector multiplication and matrix equation solving, which can be naturally mapped onto memristor crossbar arrays using the static conductance states of the devices. This enables highly parallel analog computing with improved energy efficiency for neural network inference and training.

Beyond static conductance, the dynamic switching behavior of memristors provides additional computational capabilities. Device dynamics can be exploited for applications including stateful logic for in-memory acceleration, attractor networks for associative memory, reservoir computing and spatiotemporal signal processing using transient device responses, and biologically inspired spike-timing-dependent plasticity.

This tutorial also highlights the challenges and opportunities in leveraging both static conductance and dynamic switching of resistive memory devices for next-generation AI hardware.

 

12:15 – 13:00

How Memory Powers Intelligence - From Cognition to AI Systems

Helen Li (Duke University, Durham, US)

As artificial intelligence (AI) continues to scale in power and influence, modern models increasingly mirror the complexities of human cognition. Yet, a widening gap exists between the principles of biological memory and the constraints of contemporary computing systems. This talk explores this intersection through the lens of memory. We present research that reimagines intelligent systems not just as data processors, but as experience-driven learners. Key questions include: How can systems retain and learn from past interactions? How can we prioritize what information is worth encoding? What strategies enable efficient consolidation of long-term knowledge? And how can we accelerate memory retrieval to support real-time reasoning? By drawing parallels between cognitive science and AI architecture, we highlight novel memory-centric approaches to unlocking more intelligent, scalable, and adaptive computing systems.