T5a
ESD protection for High Performance Analog and Power Management Circuits
9:30 - 17:30
ROOM FALLA
CHAIRS
Tom Van Breussegem (ICsense, Leuven, BE)
ABSTRACT
Electrostatic Discharge (ESD) resilience is a critical requirement for any circuit or ASIC entering the market. While digital I/O protection is typically addressed through foundry-provided IP, analog sensor interfaces and power management blocks — such as LDOs and DC-DC converters — often demand custom solutions from the designer. Achieving robust ESD protection requires not only hardening individual blocks but also adopting a holistic approach that spans from primary protection to secondary block-level protection.
This tutorial deals with the practice of ESD harnessing for complex mixed-signal chips and this from the circuits’ designer perspective.
PROGRAM
09:30 – 10:15
Introduction to ESD phenomena
Tom Van Breussegem (ICsense, Leuven, BE)
This first part introduces the physical mechanisms behind electrostatic discharge, including charge generation, discharge dynamics, and failure modes in ICs. Standard ESD event models (HBM, CDM, MM) are reviewed and compared in terms of stress conditions and representativeness. Transmission Line Pulse (TLP) measurements are explained as a key tool to characterize ESD robustness and extract crucial behavior.
10:15 - 11:00
ESD device models
Geert Caes (ICsense, Leuven, BE)
Behavior of devices under ESD regime is discussed with special attention paid to snapback phenomena, trigger mechanisms, holding voltage, and stability considerations. Layout-dependent effects such as current distribution, parasitics, and scaling are discussed as critical factors for reliable ESD performance.
​11:00 – 11:30
Coffee break
11:30 – 12:15
On chip ESD protection strategies
Robin Croon (ICsense, Leuven, BE)
This part covers the fundamentals of on-chip ESD protection architectures, including IO-ring concepts and power-domain protection strategies. Power clamps, diodes, MOS-based devices, and SCR-type structures are described with their operating principles and trade-offs. Integration aspects across different technology nodes and design constraints are highlighted.
12:15 – 13:00
Advanced ESD cases and examples
Geert Caes, Robin Croon & Tom Van Breussegem (ICsense, Leuven, BE)
Advanced and non‑standard ESD challenges are addressed, such as high-accuracy sensor-interfaces, mixed-voltage domains, and automotive use cases. Practical examples demonstrate hardening strategies, co-design with functional circuitry, and debugging of ESD failures. Lessons learned from real silicon cases illustrate how to achieve robust and efficient protection.
BIOSKETCHES
Tom Van Breussegem
Tom Van Breussegem received the Ph.D. degree in electronics from Katholieke Universiteit Leuven in 2012, working on Monolithic CMOS-Integrated DC-DC converters. In April 2012, he joined ICsense, Heverlee, an IC-design house specialized in power management, high voltage, and sensor interfacing. He is currently Analog Team Lead at ICsense. Tom is a senior member of IEEE and member of the ESDA (Electrostatic Discharge Association), he is leading the ESD group of TDK-ICsense. The team is responsible for the ESD sign off of numerous ASIC’s for mass production in the past years. Tom contributes to the ISSCC (2027) and ESSERC (2022-2026) Power Management TPC and the IEEE-SSCS educational webinar committee.
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Geert Caes
Geert Caes received the M.Sc. degree in electronics from Katholieke Universiteit Leuven in 2016. Immediately after graduation, he joined ICsense, Heverlee, an IC-design house specialized in power management, high voltage, and sensor interfacing, as an Analog Designer. In his current role of Senior Project Leader, he is responsible for technical project management and ensuring design quality and reliability. In 2018, he joined the ESD group of TDK-ICsense, his expertise revolves around design methodologies and concepts which increase the ESD performance of analog circuits.
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​Robin Croon
Robin Croon received the M.Sc. degree in electronics from Katholieke Universiteit Leuven in 2017. Immediately after graduation, he joined ICsense, Heverlee, an IC-design house specialized in power management, high voltage, and sensor interfacing, as an Analog Designer. In his current role of System Architect, he is responsible for the study and design of high-end integrated circuits while ensuring design quality and reliability. He is currently one of the internal ICsense experts on ESD, his expertise revolves around ESD hardening of analog circuits and tools to predict the ESD performance of an IC.