W7
MOS-AK FOSS OpenPDK
9:30 - 13:00
ROOM TURINA
CHAIRS
Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)
ABSTRACT
The 23rd MOS‑AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog‑A modeling, OpenPDKs, and open‑source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS‑AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year’s program showcases cutting‑edge developments: GaN MOS‑HEMT compact models for emerging OpenPDKs, AI/ML‑driven modeling workflows replacing manual tuning, cryogenic FD‑SOI model libraries, fully open‑source RFIC design case studies using IIC‑OSIC‑TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC‑AMS activities, promoting accessible, reproducible, and future‑ready IC design methodologies.
PROGRAM
09:30 - 09:52
ODE4EC-AMS OpenPDK: the Status and Roadmap
Wladek Grabinski (MOS-AK, CH and IHP OpenPDK, DE)
For more than 75 years, the semiconductor industry has advanced through continuous innovation supported by FOSS CAD/EDA tools form the semiconductor technology TCAD simulations and compact/SPICE modeling, Verilog‑A standardization to advanced IC design flows. Today, the industry faces a growing need for skilled engineers worldwide. The emergence of OpenPDKs creates a powerful new platform for global learning and collaboration. By combining open‑source EDA tools with openly available process design kits from SkyWater, GF in the US, Japan, and China, and the very first in Europe IHP OpenPDK initiative connects beginners, students, enthusiasts, and experienced mentors across borders. It enables hands‑on IC design education, shared research, and community‑driven innovation at a scale not previously possible. This talk highlights the role of FOSS CAD/EDA and OpenPDKs in building a global semiconductor talent ecosystem, demonstrating contributions to SPICE/Verilog‑A modeling, complete open IC BiCMOS design flows (Xschem, Qucs‑S, ngspice, Xyce, OpenVAF, OpenEMS, Magic, kLayout, OpenRoad), and selected open‑source analog, RF, and digital IC design examples.
09:53 - 10:15
Advances in Open-Source Verilog-A Compilation and Simulation
Arpad Buermen (Uni. Ljubljana, SL)
OpenVAF is a free, open-source Verilog-A compiler that serves as critical middleware in the open EDA ecosystem. It compiles Verilog-A files into OSDI-compliant shared objects, cleanly separating compact device models from simulation engines. OpenVAF enables industry-standard models -- including PSP, BSIMBULK, and BSIM-CMG -- within Ngspice and VACASK, achieving simulation speeds comparable to native C-coded implementations. While broad in coverage, some Verilog-A features remain unimplemented, with a roadmap in place to address them. VACASK is a modern analog circuit simulator built in C++ with a focus on accuracy, simplicity, and maintainability. Its OSDI-based architecture completely decouples device models from simulation algorithms, making advanced analyses straightforward to implement. A notable milestone is VACASK's transient noise analysis -- believed to be a first among open-source simulators -- where device components automatically contribute thermal, shot, and flicker noise. Harmonic balance is already supported, with periodic steady-state and RF noise analyses planned, advancing toward a fully capable open-source RF simulation platform.
10:15 - 10:37
Compact Modeling of GaN MOS-HEMTs for Open PDKs
Ashkhen Yesayan (EPFL, CH)
The development of open Process Design Kits (PDKs) for GaN technologies requires compact transistor models that are both physically grounded and computationally efficient. This work presents a charge-based compact modeling framework for GaN MOS-HEMTs, derived from analytical descriptions of device electrostatics and carrier transport. Explicit expressions for channel charge and drain current are developed, enabling robust implementation in circuit simulators through Verilog-A. The model accurately captures device behavior across subthreshold, linear, and saturation operating regimes, including short-channel effects. Validation against TCAD/COMSOL simulations demonstrates excellent agreement, making the proposed approach suitable for integration into open-source GaN PDKs and advanced circuit design workflows.
10:38 - 11:00
From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML
Roberto Tinti (Keysight, US)
This presentation outlines the transformation of device modeling through AI and machine learning, moving from complex, manual tuning workflows to automated, scalable, and intelligent systems. It explores key applications, including ML-driven model extraction, ANN-based modeling, and generative AI for flow creation. Early results demonstrate significant efficiency gains, reducing modeling cycles from months to days while improving robustness and consistency. We will highlight a progression toward assistant AI, domain agents, and fully orchestrated agentic workflows that autonomously create, optimize, and validate models. This evolution positions AI as a core enabler of faster design cycles, improved accuracy, and enhanced engineering productivity.
11:00 - 11:30
Coffee break
11:30 - 11:52
Development of Cryogenic Model Libraries for FD-SOI Transistors
Phanish Chava (AdMOS, DE)
Cryogenic electronics are gaining increasing attention for applications that require reliable operation at extremely low temperatures. Since transistor characteristics can change significantly when cooled from room temperature to cryogenic temperatures, accurate compact models are essential for predictive circuit simulation and design. In this work, we present the development of a cryogenic model library for fully depleted silicon-on-insulator (FD-SOI) transistors. We validate the library against experimental measurements over a temperature range from 8 K to 300 K. Furthermore, we demonstrate its accuracy at both device and circuit levels using single transistors, ring oscillators, and a transimpedance amplifier.
11:53 - 12:15
Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS
Georg Zachl (JKU Linz, AT)
Traditionally, Radio Frequency Integrated Circuit (RFIC) design has been confined to commercial tools due to implementation complexity and rigorous verification requirements. However, recent advances in tool development, Process Design Kit (PDK) availability, and software distribution models are positioning open-source solutions as a viable alternative. In this workshop, we will demonstrate this shift by presenting selected fully open-source RFIC designs using the IIC-OSIC-TOOLS framework. We will also critically analyze the current ecosystem, highlighting both successful implementations and the remaining gaps. Attendees will gain insights into the practical challenges of open-source workflows and the future trajectory of accessible RFIC design tools.
12:15 - 12:37
Reliability topics for the miniaturization and qualification in OpenSilicon perspective
Fernando Guarin (IEEE EDS D1, US)
Up to this point in the evolution of leading-edge Silicon CMOS technologies the qualification of the latest nodes has been carried out using the methods and targets dictated by digital/logic applications. For RF applications digital centric methodology and metrics will no longer be applicable. We will discuss the reliability impact of miniaturization and the qualification activities driven by the need to support reliable operation for RF circuit applications. The CMOS solutions for RF applications include the introduction of SOI that may introduce additional reliability considerations. The path to maintaining the advanced CMOS scaling cadence and new reliability limiting factors will be examined from the reliability perspective. We will also review the reliability requirements for RF reliability devices and applications as we prepare to introduce technologies to serve the 5G infrastructure requirements. A closer look will be given to Hot Carriers. The characterization, models and qualification methodologies will be put in the required perspective for the successful qualification and transfer of leading-edge technologies to a manufacturing environment.
12:38 - 13:00
OpenPDK MOSFET Matching Matrix IC
Juan Brito (CEITEC, BR)
A new open matrix IC and measurement approach is introduced for evaluating mismatch effects in MOS transistors. The concept uses a simple stacked‑device configuration together with a measurement method that requires only basic DC readings. This enables the separate extraction of key mismatch indicators and supports rapid characterization of design‑relevant parameters. The approach significantly accelerates data acquisition while maintaining strong correlation with reference methods. A fast addressing and biasing scheme allows individual devices to be selected within a two‑dimensional array. Presented experimental work is refering to the prototype open test chip fabricated using the IHP OpenPDK.
13:00 - 14:00
Lunch
BIOSKETCHES
Wladek Grabinski received his Ph.D. from the ITE Warsaw, in 1991. He worked at ETHZ on CMOS/BiCMOS characterization and at EPFL on compact MOSFET model development, later serving as a technical staff engineer at Motorola and Freescale in Geneva. He is now a consultant specializing in OpenPDK, coordinating SPICE modeling, device characterization, and parameter extraction for analog/RF IC design, with particular interests in high-frequency measurement, compact modeling and its Verilog-A standardization. He co-edited the book Transistor Level Modeling for Analog/RF IC Design, contributed to the Compact/SPICE Modeling Chapter of the Springer Handbook of Semiconductor Devices, and authored 70+ papers. Furthermore, he also contributes to IEEE EDS, ESSDERC, and MIXDES and manages the MOS-AK association since 1999.
Árpád Bürmen received his PhD in electrical engineering from University of Ljubljana in 2003 where he is a tenured professor of electrical engineering. His research interests include analog circuits, circuit simulation, design automation, and optimization algorithms. He co-authored the SPICE OPUS circuit simulator and is the lead developer of the VACASK circuit simulator, the Verilog-A Distiller model converter, and the PyOpus design automation library. He published over 40 papers in international journals and co-authored a book titled "Circuit simulation with SPICE OPUS : theory and practice" published by Birkhäuser (Springer) in 2009.
Ashkhen Yesayan received the M.S. and Ph.D. degrees in physics from Yerevan State University, Yerevan, Armenia, in 1994 and 2005, respectively. Since 2011, she has been a Senior Researcher with the Institute of Radiophysics and Electronics, NAS RA, Yerevan, Armenia, where she has been the Scientific Secretary since 2014. Her current research interests include compact modeling and photovoltaics of nanowire.
Roberto Tinti is a leader in device modeling and advanced measurement technologies with 25+ years of experience. He holds a Ph.D. from Delft University of Technology and has been with HP/Keysight since 1999, driving innovations in device characterization and advancing the IC-CAP platform, including optimization and GaN model extraction. He is now leading AI-driven device modeling, integrating machine learning and automation to accelerate model extraction and improve accuracy. As Product Owner for Keysight’s device modeling software, he drives the evolution of EDA solutions to address emerging challenges and scale intelligent, customer-centric workflows.
Phanish Chava received his MSc and PhD from TU Dresden, specializing in nano- and microelectronics, in 2018 and 2025, respectively. He subsequently worked as a postdoctoral researcher at Forschungszentrum Jülich, Germany, where he focused on cryogenic measurement and modeling of advanced transistor nodes. In 2026, he joined AdMOS as the CTO, where he leads the development of transistor models and low-frequency noise measurement systems.
Georg Zachl completed his technical secondary education at HTL Steyr in 2013, followed by a Bachelor’s degree (2018) and a Master’s degree (2020) in Electronics and Information Technology (ELIT) from Johannes Kepler University (JKU) Linz. He has been a researcher and PhD candidate at JKU Linz since 2020, focusing on radio frequency integrated circuit design with a specialized emphasis on mm-Wave receiver and transmitter architectures. Additionally, Georg serves as a maintainer of IIC-OSIC-TOOLS, a collection and distribution of open-source software for IC design.
Fernando Guarin retired in July 2022 as a Distinguished Member of Technical Staff at Global Foundries in East Fishkill New York where he led the reliability team responsible for the qualification of 5G technologies. In 2015 he retired from IBM’s Semiconductor Division after 27 years as Senior Member of Technical Staff. He earned his BSEE from the “Pontificia Universidad Javeriana”, in Bogotá, Colombia, the M.S.E.E. degree from the University of Arizona, and the Ph.D. in Electrical Engineering from Columbia University, NY. He has worked in microelectronic reliability for over 42 years. From 1980 until 1988 he worked in the Military and Aerospace Operations division of the National Semiconductor Corporation. In 1988 he joined IBM’s microelectronics division where he worked in the reliability physics and modeling of Advanced Bipolar, CMOS and Silicon Germanium BiCMOS technologies. Most recently he was the leader of the team qualifying GlobalFoundries RF 5G technology offerings. Dr. Guarín is an IEEE Life-Fellow, Distinguished Lecturer for the IEEE Electron Device Society EDS, where he has served in many capacities including member of the IEEE’s EDS Board of governors, chair of the EDS Education Committee, Secretary for EDS. He was the EDS President 2018-2019. He is the Division I Director 2026-2027 for IEEE.
Juan Pablo Martinez Brito, PhD, is a semiconductor engineering leader with 15+ years bridging design, test, and manufacturing. Experienced in device modeling, wafer-level characterization, and analog IC design across CMOS advanced technology nodes. Cross-site test and modeling programs leader, increasing validation capacity, improving yield, and enabling first-time-right silicon for high-volume RFID products. Strong background in test automation, reliability analysis, and NPI, with a passion for mentoring engineers and connecting R&D to production. Author of 25+ publications and patents in the U.S. and Brazil, driving innovation at the intersection of process, design, and product engineering.