09:30 - 11:00

Successive Approximation ADCs: From compact low-power data conversion techniques to identifying system level bottlenecks.

Harijot Singh Bindra (University of Twente, Enschede, NL)

The advancements in SAR ADCs in the last two decades has enabled energy-efficient data conversion for range of applications from wide bandwidth to those requiring sub-microwatt power. The academic Figure of Merit (FoM)-race in ADCs resulting from this, however, do not capture the design challenges of the ADC’s peripheral circuitry especially input signal. The tutorial will present some advancements in SAR ADCs that enabled such range of applications from GHz wide conversion to a FoM below 1fJ/conv-step. The tutorial will further aim at identifying some of the system level challenges when integrating SAR ADCs to the peripheral circuitry.

 

11:00 - 11:30

Coffee break

 

11:30 - 13:00

Number of Oscillation Cycles (NOC): A New Paradigm for Closed-Loop VCO-based Comparison

Qiang Li, (TUHH, Hamburg, DE)

SAR ADCs with time-based comparator have attracted significant interest in recent years. This talk introduces the concept of oscillation-cycle information in VCO-based comparators. With rigorous analysis, the number of oscillation cycles (NOC) can be generally exploited as a parallel coarse quantization with a large signal, and/or as a quantitative indication of metastability with a small signal. Moreover, the NOC is inherent and of little cost in hardware, power and area. The demonstrated VCO ADCs exhibit significantly enhanced linearity and robustness, comparing with their voltage-domain counterparts. This talk discusses also a closed-form metastability analysis of VCO-based comparator, introducing the metastability depth as a quantitative measure of metastability.

 

13:00 - 14:00

Lunch

 

14:00 - 15:30

Digital to Radio Frequency Conversion Techniques

Shiyu Su (University of Waterloo, CA)

Direct digital-to-RF conversion is emerging as a promising transmitter paradigm for next-generation wireless systems, enabled by continued CMOS scaling and advances in high-speed data converters and signal processing. This tutorial provides a comprehensive introduction to digital-to-RF conversion techniques, focusing on two main themes: (1) high speed, high-resolution digital-to-analog converter (DAC) design techniques, and (2) reconfigurable, high-dynamic range digital transmitters/RF-DACs enabled by reconstruction-filter-response engineering and powerful digital or digital-like signal processing. It will further cover techniques for bandwidth extension, dynamic-range enhancement, and power efficiency improvement through design examples, while highlighting recent trends and practical challenges in direct-RF transmitter architectures and implementations.

 

15:30 - 16:00

Coffee break

 

16:00 - 17:30

Highly Linear Delta-Sigma Analog to Digital Converters: From Discrete Time to Continuous-Time Architectures

Francesco Conzatti (Infineon Technologies Austria, AT)

Analog to Digital Converters (ADC) are key components in several applications, for instance sensor interfaces, communication systems, radar sensing, just to name a few. ADC non-linearity leads to degraded performance at system level, for instance higher Bit-Error-Rate (BER), degraded Error Vector Magnitude (EVM) or audible artifacts (audio). In this context, Delta-Sigma Modulators (DSMs) are proven to achieve very demanding linearity requirements and several techniques have been published in the State-of-the-Art in order to address DSM non linearities and in particular to linearize the feedback Digital to Analog Converter (DAC), which is the key component to guarantee overall signal fidelity. Dynamic Element Matching (DEM) is effective as a background linearization technique, but leads to an increase of both current consumption and loop delay. Another popular approach is calibrating the DAC, which complicates the ADC system integration and is often proposed as an off-chip background solution. Single-Bit DAC designs reach outstanding linearities, but their application is usually limited to low-speed and low-bandwidth scenarios. Recent works on Highly Linear ADCs tackle these issues and propose converter architectures that do not need neither calibration nor DEM, but still can reach very competitive performance in terms of linearity for both low-speed and high-speed scenarios. In this context, this tutorial will cover recent advancements on inherently linear Delta-Sigma ADCs, ranging from Discrete-Time (DT) to Continuous-Time(CT) architectures.