9:30-10:15

Evolving Cryo-CMOS Chip for Quantum Computing

Edoardo Charbon (EPFL, CH)

The core of a quantum computer is generally an array of qubits and classical electronics for its control; it operates on the qubits with nanosecond latency and a very low noise. Classical electronics is generally operating at room temperature, however recently, we have proposed to move it closer to the qubits and to operate at cryogenic temperatures to improve compactness and reliability. This proposal has been adopted by many in academia and industry. Though, new constraints have emerged in the electronics, especially in terms of noise and power dissipation, due to the extremely weak signals generated by quantum devices that require highly sensitive circuits and systems, along with very precise timing capability. We advocate the use of fully-integrated CMOS chips to achieve these goals, whereas the circuits are operated at 2-10K. We believe that these, collectively known as cryo-CMOS circuits, will make future qubit arrays scalable, enabling a faster growth in qubit count. In the talk, the challenges of designing and operating complex circuits and systems at deep-cryogenic temperatures will be outlined, along with preliminary results achieved in the control of quantum devices by ad hoc integrated circuits that were optimized to operate at low power in these conditions. The talk will conclude with a perspective on the field and its trends.

 

10:15 - 11:00

Cryo-CMOS designs for superconducting qubit-based quantum computers:  challenges and solutions

Daniel Friedman (IBM, US)

CMOS designs operating at cryogenic temperatures offer the promise of key benefits for the realization of superconducting qubit-based scaled quantum computing systems, but also present significant challenges.  In this presentation, a system framework for the realization of a scalable quantum computing system leveraging cryogenic CMOS design elements will be discussed. This system framework will provide the context for considering the requirements for cryogenic CMOS implementations. Finally, cryogenic CMOS design examples addressing those requirements within the described system context and pointing toward scalable qubit interface electronics solutions will be presented.

 

11:00 - 11:30

Coffee break

 

11:30 - 12:15

QSOI®: an in-foundry silicon quantum technology to access Fault-Tolerant Quantum Computing

Jean-Charles Barbé (Quobly, FR)

Leveraging industrial semiconductor foundries provides a pathway to Fault-Tolerant large-scale quantum computing, as they offer the required process uniformity, yield, and scalability. This approach also enables the integration of CMOS on a quantum chip, which is critical to reduce the wiring complexity inherent in the part of the quantum computer that operates at cryogenic temperatures within a cryostat. First, we will introduce the QSOI® quantum technology platform, which was developed from the outset for accessing the Fault-Tolerant Quantum Computing area. We will then discuss the specific challenges that need to be overcome.

 

12:15 - 13:00

Cryogenic Integrated Circuits for Trapped Ion Quantum Computer and Scalability Challenges

Vadim Issakov (TU Braunschweig, DE)

This talk discusses in a systematic way the challenges and system-level aspects related to design of integrated circuits for a trapped ion quantum computer. First, system level aspects and physics review of a trapped ion quantum computer operation is given. Particularly, near-field microwave gates are described (on example of Be+, Ca+ and Yb+ ions). Various parts of the system are presented and discussed: electronics for DC electrodes, RF and microwave drivers. Next, we focus on the microwave drivers and discuss the architecture including microwave power amplifiers with envelope shaping along with integrated direct digital synthesizers (DDS). Afterwards, we discuss the shuttling controller including DACs and high-voltage signal conditioning to implement the shuttling motion of the ions on the quantum processor chip. Further, we discuss the high-voltage signal generation for the RF electrodes. Finally, we summarize and make an outlook towards high level scalability, electronics partitioning considerations, i.e. what can stay at room temperature and what should go to cryo-temperatures and practical realization bottlenecks.