W8
Recent advances in millimeter-wave and 6G hardware design
using BiCMOS and SiGe technologies
9:30 - 13:00
ROOM MAGNA
CHAIRS
Philippe Ferrari (University Grenoble alpes, Grenoble, FR)
Christophe Gaquière (MC2 Technologies, Lille, FR)
ABSTRACT
This workshop focuses on recent advances in millimeter-wave and 6G hardware design using BiCMOS and SiGe technologies, within the framework of the SHIFT Chips EU Project (Sustainable tecHnologies enablIng Future Telecom applications). Overall, it provides a comprehensive overview of enabling technologies for next-generation high-frequency communication systems. It emphasizes system-level optimization through co-design of circuits, antennas, and signal processing. Following circuits design are addressed:
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Ultra-low-jitter frequency generation techniques achieving record performance for high spectral purity applications.
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Novel modeling and design approaches for coupled lines that enable compact and efficient D-band components.
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Multi-antenna transceivers leveraging spatial processing, presented to relax system constraints and improve performance.
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Integration challenges through compact Ka-band front-end modules combining SiGe and GaN technologies.
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Advanced low-noise amplifier (LNA) design methodologies in 55-nm BiCMOS, including modeling and measurement insights.
Power amplifier (PA) designs trade-offs for 6G FR3 systems, covering efficiency, linearity, and stability.
PROGRAM
SESSION 1
09:30 – 10:00
Breaking the Jitter Barrier: Ultra-Low-Jitter Frequency Generation in 55-nm BiCMOS for mm-Wave Systems
Salvatore Levantino (Politecnico di Milano, IT)
Within the SHIFT project, we present a frequency generation suite in 55-nm BiCMOS. The 10-12 GHz PLL core achieves record integrated jitter of 14.9 fs (integer-N) and 25.4 fs (fractional-N). This is enabled by a power-gated LC oscillator (PGO) acting as a DTC and a series-resonance DCO. A 56-76 GHz sextupler complements the PLL, featuring a digitally calibrated tripler with >40-dB fundamental rejection. These components set new benchmarks for high-spectral-purity signal generation, targeting 6G backhaul and satellite communication requirements.
10:00 – 10:30
Coupled-lines and their Applications in Millimeter-wave BiCMOS
Joao E. Gentil Lé (University Grenoble Alpes, FR; FHNW, CH)
As wireless systems push for higher data rates using millimeter-wave frequencies, coupled-lines (Clines) emerge as compact, high-performance alternatives to lumped elements—yet their modeling is absent from standard Process Design Kits (PDKs). In this talk, we introduce a general modeling approach for Clines in BiCMOS technology, introducing “Clines Charts” as a design-oriented abacus. Building on this framework, we demonstrate multiple fabricated D-band (110–170 GHz) Clines-based building blocks—including couplers, matching networks, variable attenuators, switches, phase shifters, and variable power splitters—achieving state-of-the-art performance.
10:30 – 11:00
Multi-Antenna Transceivers Exploiting Spatial Processing.
Dominique Morche (CEA-Leti, FR)
While the carrier frequency is reaching higher mmwave, the number of required antenna elements increases, thereby impacting the complexity of the system. This, however come with some additional degree of freedom. This talk will detail how spatial processing can be exploited in multi-antenna system to relax the requirements of the transceiver building blocks. The basic principle and state of the art will be first presented. A new approach, relying of spatial shaping of the noise, will be described. The benefit on a digital beamforming transmitter with 8 antennas will be shown. Some perspectives to further exploit the approach will be drawn at the end.
11:00 – 11:30
Coffee break
SESSION 2
11:30 – 12:00
Ka-band Front End Module Integration Based on SiGe and GaN Custom Chipsets.
Alessandro Fonte (SIAE, IT)
The integration of front-end modules in phased arrays is increasing with LEO and NTN applications. While many silicon beamforming ICs exist, custom specifications still require dedicated MMIC developments. This work proposes a compact module integrating five MMICs within a 30 × 30 mm² footprint. It includes a 0/90° Wilkinson splitter, a SiGe vector modulator, an LNA, and a dual GaN PA delivering 27 dBm per channel. Control and monitoring are handled by a compact 5 × 5 mm² SPI-controlled chip. The module is encapsulated using a PCB carrier-grade process compatible with SMT assembly.
12:00 – 12:30
D-band Low-Noise-Amplifier design in 55-nm SiGe BiCMOS
Pierre-Louis Hellier (University Grenoble Alpes, FR)
MmW design in IC technologies faces challenges due to the transistors low gain and the propagation effect within the passive components. This presentation summarizes the work done on LNAs within the SHIFT project. Components modeling and measurements are described. Design metrics for LNA are introduced and a flexible workflow is proposed. LNAs developed for the project are detailed including the HBT sizing and biasing, the amplifier topology and the impedance matching strategies. Finally, the LNAs measurements are presented and discussed.
12:30 – 13:00
6G FR3 Power Amplifier Design considerations for mobile communications in B55X technologies
Nathalie Deltimple (IMS Bordeaux, Bordeaux INP, FR).
This work covers design considerations for integrated SiGe power amplifiers in 6G FR3 phased-array systems. Regarding to the PA, a particular attention is given to performance trade-offs involving output power, efficiency, linearity, and stability in highly integrated architectures. Several SiGe PA architectures will be considered: cascade and differential PA, balanced PA, and load-modulated balanced amplifier (LMBA). This talk will also cover the amplitude and phase control to give an overview of the SiGe BFIC performances. Simulations and measurement results will be presented.
BIOSKETCHES
Salvatore Levantino is a Professor of Electronics at Politecnico di Milano, Italy, specializing in RF/millimeter-wave integrated circuits and frequency synthesizers. He has co-authored over 200 peer-reviewed papers and the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press). His professional service includes roles on the Technical Program Committees of ISSCC, ESSERC, and RFIC Symposium, and a term as a Distinguished Lecturer of the IEEE SSCS. He is currently an Associate Editor for the IEEE Open Journal of the Solid-State Circuits Society.
Joao E. Gentil Lé received the B.S. and M.Sc. degrees in Electrical Engineering from the Polytechnic School, Universidade de São Paulo (USP), São Paulo, Brazil, in 2021 and 2023, respectively. He is currently a research associate at Fachhochschule Nordwestschweiz (FHNW), Windisch, Switzerland, and is pursuing the Ph.D. degree with TIMA Laboratoire, Université Grenoble Alpes (UGA), Grenoble, France. He worked as an application engineer at Keysight Technologies, São Paulo, Brazil. During his time at USP, he developed an antenna measurement system for V- and W-band frequencies. In TIMA, his research focused on D-band RFIC design. In FHNW, he works with co-packaged optics.
Dominique Morche received his engineering diploma from ENSERB in 1990 and the Ph.D degree in Electronics from the UGA in 1994. From 1994 to 2001 he was employed by Orange Labs as a research engineer. He was involved in both circuit and system design for telecom applications. In 2001, Dr. Morche joined LETI as a research engineer and project leader in RF systems for a wide range of applications. Since 2015 he is a Research Director. He has authored and co-authored more than 100 international journal and conference papers, hold more than 20 patents. He is or has been a member of the scientific committee of several conferences (among ESSCIRC, ISSCC, …) and serve as a reviewer for several journals. His current field of interest are low power communication systems, Impulse Radio, RF architecture simulation and optimization and power efficient mmw systems.
Alessandro Fonte Head of Microwave Technologies Department and Member of Technical Staff of SIAE Microlettronica. Dr. Fonte received the Ph.D. degree in Information Engineering from the University of Pisa, Italy, in 2008. He is the contact person and Workpackage leader in several Funded European Projects in which SIAE is one of the corporate partners. He has authored several papers in peer-reviewed international journals and conference proceedings and two book chapters. His current research interests include the development of the SIAE activities in MMIC, RFIC, and System-in-Package design (SiP) with operating frequencies up to D-band.
Pierre-Louis Hellier received the M.Eng. degree in integrated electronic systems from Phelma, Grenoble Institute of Technology, France, in 2023. He is currently pursuing the Ph.D. degree with the TIMA Laboratory, Grenoble Alpes University, and IM2NP Laboratory, University of Toulon. His research interests include design, modeling, and characterization of millimeter-wave integrated circuit. He has authored or co-authored 4 international & national journals and conferences articles.
Nathalie Deltimple, member IEEE (SM’05-M’09), received the Ph.D. degree in Electrical Engineering from University of Bordeaux, France in 2005. She joined Bordeaux INP/ENSEIRB-MATMECA in the Electronics Department and the IMS Laboratory in 2006, where she is currently Professor and Deputy Director of IMS Laboratory, in charge of industrial partnerships. Her main areas of research are RF and microwave integrated circuit for wireless communications and space application, the development of integrated efficiency enhancement and linearization techniques. She is currently involved in European and national scientific programs about IC PA design in CMOS, BiCMOS and GaN technologies for 6G applications (Ka-band and D-band) as well as linearization techniques. Prof. Deltimple is involved in the technical program committees of IEEE SSC, MTT and CAS societies conferences (ESSERC, RWW/PAWR), ICECS, NEWCAS) and EuMA EuMW. She was the General Chair of ICECS 2018, TPC chair of IWS 2016, General TPC Chair EuMW 2019, Chair of EuMIC 2024 and will be co-chair of ISCAS 2027 and ESSERC 2028. She serves as a reviewer for various IEEE conference and journal.